verilog HDL 进击之路

Verilog 进击之路 - 夯实基础第一节之结构化设计

       随着数字电路设计的复杂化和专业化，传统的电路设计逐渐没落，Verilog HDL逐渐走入历史舞台。好多人并非不会Verilog，而是缺少细致的了解。最近一直在看 A Guide to Digital Deisgn and Synthesis  这本书，感受许多的疑点获得解决，正好分享出来共勉。

　　对设计者来说，最重要的是如何实现设计和优化设计。以下是 A typical design flow. 

1. specifications are written first. specificitions 简要描述了设计电路的function, interface, overall architecture.
2. a behavioral description 来分析设计电路的function, peoformance,compliance to standards and high-level issues.
3. behavioral description converted to RTL description. 
4. RTL description converted to gate-level netlist by logic synthesis tools.
5. The netlist is input to an automatic place and route tool, which creats a layout.

　　在进行Verilog design时，必须follow design methodology and basic hierarchical modeling.

         1.Design methodology: a  combination of top-down and bottom-up.  先构建设计的架构，进行top_level and sub_block的逻辑关系实现，而后在sub_block中build leaf cell and optimized circuits in cell，从而实现top and bottom 的同时设计. 

         2. Basic hierarchical modeling: a module is the basic buliding block in verilog. 共有四个design level能够使用。behavioral level   dataflow level   gate level  switch level.

　　  3. Test bench include stimulus/monitor and design blocks,搭建仿真环境也要follow the design rules.

 

　　本次重点是了解一个verilog design的层次化结构是如何展开的，下节将会阐述做为 basic block 的 module framework是如何实现的.