四选一多路选择器

module cy4(out,i0,i1,i2,i3,s1,s0); output out; input i0,i1,i2,i3; input s1,s0; reg out; always @(s1 or s0 or i0 or i1 or i2 or i3) begin case({s1,s0}) 2'b00: out = i0; 2'b01: out = i1;

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