verilog实例化时端口信号传递规则

module hello_top( input clk_t, input rst_t, input rxd_t, output txd_t ); uart_send u_uart_send( .clk (clk_t), .rst (rst_t), .txd (txd_t) ); endmodule module uart_send( input clk, input rst, output txd

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