Vivado dubug core被删除解决方法（The debug hub core was not detected, Dropping logic with cellname:'xxx'）
情景描述： 使用Vivado 2017.4书写Verilog代码，并且创建debug core进行信号抓取。添加完debug core并成功Run Implementaion,在IMPLEMENTATION的结构图中可以看到相应的ila_core和hub都已经建立。在生成bit文件的时候出现warning告知debug core被丢掉了，因为没有在设备上找到相应的内容，警告截图如下： 虽然bit文
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